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esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 1/21 fast ultra high-psrr, low-noise, low-dropout, 150ma micropower cmos linear regulator general description the emp891x series is a family of cmos linear regulators, which include emp8915 and emp8916, featuring ultra-high power supply rejection ratio, low output voltage noise, low dropout voltage, low quiescent current and fast transient response. emp891x guarantees delivery of 150ma output current, and supports preset 1.2v, 1.3v, 1.5v, 1.8v, 2.5v, 2.8v, 2.85v output voltage versions. based on its low quiescent current consumption and its less than 1 a shutdown mode of logical operation, the emp891x series are ideal for battery-powered applications. the ground current increases only slightly in dropout, further prolonging the battery life. emp891x series provide fast turn-on by using dedicated circuitry to pre-charge an optional external bypass capacitor. this bypass capacitor is used to reduce the output voltage noise without adversely affecting the load transient response. the high power supply rejection ratio of the emp891x holds well for low input voltages typically encountered in battery- operated systems. the regulator is stable with small ceramic capacitive loads (2.2f typical). additional features include regulation fault detection, bandgap voltage reference, constant current limiting and thermal overload protection. available in miniature sot-25, sot-26 and tdfn-6 packages, the emp891x series are suitable for portable appliances. emp products is rohs compliant. features ? miniature sot-25, sot-26 and tdfn-6 packages ? 150ma guaranteed output current ? 75db typical psrr at 1khz (60db typical at 10khz) ? 30v rms output voltage noise (10hz to 100khz) ? 65mv typical dropout at 150ma ? 106a typical quiescent current ? less than 1 a typical shutdown mode ? fast line and load transient response ? 80s typical fast turn-on time ? 2.5v to 5.5v input range ? stable with small ceramic output capacitors ? over temperature and over current protection ? 2% output voltage tolerance ? 1% output voltage tolerance for vout 1.5v applications ? wireless handsets ? pcmcia cards ? dsp core power ? hand-held instruments ? battery-powered systems ? portable information appliances
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 2/21 connection diagrams tdfn-6(top view) note: version also available for pin #1 as fault pin and pin #5 as shdn pin sot-25(top view) sot-26(top view) order information emp8915-xxfe06grr xx operation code fe06 tdfn-6 package nrr rohs & halogen free package commercial grade temperature rating: -40 to 85c package in tape & reel emp8915-xxvf05grr xx operation code vf05 sot-25 package grr rohs package commercial grade temperature rating: -40 to 85c package in tape & reel emp8916-xxvc06grr xx operation code vc06 sot-26 package grr rohs package commercial grade temperature rating: -40 to 85c package in tape & reel
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 3/21 marking & packing information marking no. of pin en cc fault package new old (8935/8915) vout product id date code; p621/p611 1.2 emp8915-12vf05grr date code; ---/p612 1.3 emp8915-13vf05grr date code; p624/p614 1.5 emp8915-15vf05grr date code; p627/p617 1.8 emp8915-18vf05grr date code; p62e/p61e 2.5 emp8915-25vf05grr date code; p62h/p61h 2.8 emp8915-28vf05grr 5 y y n sot-25 date code; ---/p61n 2.85 emp8915-2qvf05grr 1.2 emp8916-12vc06grr 1.3 emp8916-13vc06grr 1.5 EMP8916-15VC06GRR 1.8 emp8916-18vc06grr 2.5 emp8916-25vc06grr 2.8 emp8916-28vc06grr 6 y y y sot-26 2.85 emp8916-2qvc06grr 1.2 by request 1.3 by request 1.5 by request 1.8 by request 2.5 by request 2.8 by request 5 y y n tdfn-6 2.85 by request
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 4/21 1.2 by request 1.3 by request 1.5 by request 1.8 by request 2.5 by request 2.8 by request 6 y y y tdfn-6 2.85 by request typical application
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 5/21 pin functions name sot-25 sot-26 tdfn-6 function vout 5 6 4 output voltage feedback . vin 1 1 3 supply voltage input . require a minimum input capacitor of close to 1f to ensure stability and sufficient decoupling from the ground pin. gnd 2 2 2 ground pin . nc 5 or n/a no connection cc 4 4 6 compensation capacitor . connect an optimum 33nf noise bypass capacitor between the cc and the ground pins to reduce noise in vout. shdn 3 3 1 or 5 shutdown input. set the regulator into the disable mode by pulling the shdn pin low. to keep the regulator on during normal operation, connect the shdn pin to vin. the shdn pin must not exceed vin under all operating conditions. fault 5 n/a or 1 fault detection output. the fault pin goes low when the voltage regulating function fails. because the fault pin connects to the open-drain output of a nmos transistor, a typical 100k pull-up resistor is required to provide the necessary output voltage. the fault pin enters the high impedance state during shutdown and it should be connected to ground if unused.
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 6/21 absolute maximum ratings (notes 1, 2) vin, v out , v shdn , v set , v cc , v fault -0.3v to 6.5v power dissipation (note 3) storage temperature range -65c to160c junction temperature (tj) 150c lead temperature (10 sec.) 260c esd rating human body model (note 5) 2kv thermal resistance ( ja) tdfn-6 (note 3) sot-25 250c/w sot-26 250c/w operating ratings (note 1, 2) temperature range -40c to 85c supply voltage 2.5v to 5.5v electrical characteristics unless otherwise specified, all limits guaranteed for v in = v out +0.5v (note 6), v shdn = v in , c in = c out = 2.2f, c cc = 33nf, t j = 25c. boldface limits apply for the operating temperature extremes: -40c and 85c. symbol parameter conditions min typ (note 7) max units v in input voltage 2.5 5.5 v output voltage tolerance 100a i out 150ma v in = v out (nom) +0.5v, (note 6) -2 +2 % of v out (nom) v otl 1.5v output voltage tolerance 100a i out 150ma v in = v out (nom) +0.5v, (note 6) -1 +1 % of v out (nom) i out maximum output current average dc current rating 150 ma i limit output current limit 165 280 ma i out = 0ma 106 210 a supply current i out = 150ma 145 i q shutdown supply current v out = 0v, shdn = gnd 0.001 i out = 1ma 0.03 i out = 50ma 22 v do dropout voltage (note 4), (note 6) i out = 150ma 65 mv f = 100hz 74 f = 1khz 75 f = 10khz 60 psrr power-supply rejection ratio vin=3.5v, v out =2.5v i out =50ma f = 100khz 36 db line regulation i out = 1ma, (v out + 0.5v) v in 5.5v, (note 7) 0.02 %/v v out load regulation 100a i out 150ma 0.0004 %/ma e n output voltage noise i out = 10ma, 10hz f 100khz 30 v rms v ih , (v out + 0.5v) v in 5.5v (note 6) 1.2 v shdn shdn input threshold v il , (v out + 0.5v) v in 5.5v (note 6) 0.4 v i shdn shdn input bias current shdn = gnd or vin 0.1 100 na v fault fault detection voltage v out 2.5v, i out = 150ma (note 8) 95 mv
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 7/21 fault output low voltage i sink = 2ma 0.2 v i fault fault off-leakage current fault = 3.6v, shdn = 0v 0.1 100 na thermal shutdown temperature 165 t sd thermal shutdown hysteresis 30 t on turn-on time v out at 95% of final value 80 s note 1: absolute maximum ratings indicate limits beyond which damage may occur. electrical specifications are not applicable when the device is operated outside of its rated operating conditions. note 2: all voltages are defined and measured with respect to the potential at the ground pin. note 3: maximum power dissipation for the device is ca lculated using the following equations: ja a t - j(max) t d p = where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction-to-ambient thermal resistance. e.g. for the sot-25 package ja = 250c/w, t j(max) = 150c and using t a = 25c, the maximum power dissipation is found to be 500mw. the derating factor (-1/ ja ) = -4mw/c, thus below 25c the power dissipation figure can be increase d by 4mw per degree, and similarity decreased by this factor for temperatures above 25c. the value of the ja for the tdfn package is specifically dependent on the pcb trace area, trace material, and the number of layers and thermal vias. note 4: dropout voltage is measured by reducing v in until v out drops 100mv from its nominal value at v in -v out = 0.5v. dropout voltage does not apply to the regulator versions with v out less than 2.5v. note 5: human body model: 1.5k in series with 100pf. note 6: condition does not apply to input voltages below 2.5v since this is the minimum input operating voltage. note 7: typical values represent the most likely parametric norm. note 8: the fault detection voltage is specified for the input to output voltage differential at which the fault pin goes active low.
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 8/21 functional block diagram fig.1. emp891x functional block diagram
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 9/21 typical performance characteristics unless otherwise specified, vin = v out (nom) + 0.2v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. psrr vs frequency psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) frequency (hz) psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) psrr (db) psrr (db) psrr (db) psrr (db) psrr (db) psrr (db)
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 10/21 typical performance characteristics unless otherwise specified, vin = v out (nom) + 0.2v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) psrr vs frequency psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) frequency (hz) psrr vs frequency frequency (hz) psrr vs frequency frequency (hz) psrr (db) psrr (db) psrr (db) psrr (db) psrr (db) psrr (db)
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 11/21 typical performance characteristics unless otherwise specified, vin = v out (nom) + 0.2v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) line transient load transient enable response (vin=v out +0.2v) line transient load transient enable response (vin=4.2v) v out =2.8v, i out =1ma v out (10mv/div) v out =2.8v, vin=3v v out , 10mv/div 50ma/div vin (v), tr=tf=30 s i out , 1ma~150ma 3.0 3.6 v out =2.8v, i out =150ma v out (10mv/div) vin (v), tr=tf=30 s 3.0 3.6 v out =2.8v, vin=4.2v v out , 10mv/div 50ma/div i out , 1ma~150ma 400 s/div 400 s/div 20 s/div v shdn , 1v/div v out , 1v/div i out =150ma 400 s/div 400 s/div 20 s/div v shdn , 1v/div v out , 1v/div i out =150ma
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 12/21 typical performance characteristics unless otherwise specified, vin = v out (nom) + 0.2v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) dropout voltage vs. load current fault detect threshold vs. load current supply current vs. input voltage supply current vs. load current supply current (a) fault detect threshold (mv) load current (ma) load current (ma) dropout voltage (mv) supply current (a) input voltage (v) load current (ma)
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 13/21 typical performance characteristics unless otherwise specified, vin = v out (nom) + 0.2v, c in = c out = 2.2f, c cc = 33nf, t a = 25c, v shdn = vin. (continued) line regulation load regulation vin (v) load current (ma) v out deviation (%) i out =1ma v out deviation (%) vin=v out + 0 . 5 v
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 14/21 application information general description referring to figure 1 of the functional block diagram, the emp891x is designed in such a way that a negative feedback control is used to perform the desired voltage regulating function. the negative feedback is formed by using feedback resistors (r1, r2) to sample the output voltage for the non-inverting input of the error amplifier, whose inverting input is set to the bandgap reference voltage. due to its high open-loop gain, the error amplifier operates to ensure that the sampled output feedback voltage at its non-inverting input is virtually equal to the preset bandgap reference voltage. these feedback resistors can be either internal or external to the emp891x, depending on whether a preset or an adjustable output voltage version is being used. to control the amount of current reaching the output, the error amplifier compares the voltage difference at its inputs and produces an appropriate driving voltage to the p-channel mos pass transistor. if there are changes in the output voltage due to load changes, the feedback resistors register such changes to the non-inverting input of the error amplifier. the error amplifier then adjusts its driving voltage to maintain virtual short between its two input nodes under all loading conditions. hence, the regulation of the output voltage is achieved as a direct result of the error amplifier keeping its input voltages equal. this negative feedback control topology is further augmented by the shutdown, the fault detection, and the temperature and current protection circuitry. output capacitor to take advantage of the savings in cost and space as well as the superior filtering of high frequency noise, the emp891x is specially designed for use with ceramic output capacitors of as low as 2.2f. capacitors of higher value or other types may be used, as long as its equivalent series resistance (esr) is restricted to less than 0.5 . the use of larger capacitors with smaller esr values is desirable for applications involving large and fast input or output transients, as well as for situations where the application systems are not physically located immediately adjacent to the battery power source. typical ceramic capacitors suitable for use with the emp891x are x5r and x7r. the x5r and the x7r capacitors are able to maintain their capacitance values to within 20% and 10%, respectively, as the temperature increases. no-load stability the emp891x can maintain stable operation during no-load conditions, a required feature for some applications such as cmos ram keep-alive operations. input capacitor a minimum input capacitance of 1f is required for emp891x. the capacitor value may be increased without limit. caution should be taken as the instability may result from long supply lead inductance coupling to the output through the gate capacitance of the pass transistor. this will establish a pseudo lcr network, and is likely to happen under high current conditions or near dropout. a 10f tantalum input capacitor will dampen the parasitic lcr action thanks to its high esr. however, cautions should be exercised to avoid regulator short-circuit damage when tantalum capacitors are used, for they are prone to fail in short-circuit operating conditions. compensation (noise bypass) capacitor to reduce the output voltage noise of the emp891x, the bypass capacitor c cc (33nf optimum) can be connected between pin cc and the ground. because pin cc connects directly to the high impedance output of the bandgap reference circuit, the level of the dc leakage currents in the c cc capacitors used will adversely reduce the regulator output voltage. this sets the dc leakage level as the key selection criterion of
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 15/21 application information (continued) the c cc capacitor types for use with the emp891x. npo and cog ceramic capacitors typically offer very low leakage. although the use of the c cc capacitors does not affect the transient response, it does affect the turn-on time of the regulator. tradeoff exists between output noise level and turn-on time when selecting the c cc capacitor value. power dissipation and thermal shutdown excessive power dissipation may cause thermal overload, and hence the increase of the ic junction temperature beyond a safe operating level. the emp891x relies on dedicated thermal shutdown circuitry to limit its total power dissipation. an ic junction temperature t j exceeding 165c will trigger the thermal shutdown logic, turning off the p-channel mos pass transistor. the pass transistor turns on again after the junction cools off by about 30c. when continuous thermal overload conditions persist, this thermal shutdown action then results in a pulsed waveform at the output of the regulator. the concept of thermal resistance ja (c/w) is often used to describe an ic junction?s relative readiness in allowing its thermal energy to dissipate to its ambient air. an ic junction with a low thermal resistance is preferred because it is relatively effective in dissipating its thermal energy to its ambient, thus resulting in a relatively low and desirable junction temperature. the relationship between ja and t j is as follows: t j = ja (pd) + t a t a is the ambient temperature, and p d is the power generated by the ic and can be written as: p d = i out (v in - v out ) as the above equations indicate, it is desirable to work with ics whose ja values are small such that t j does not increase strongly with p d . to avoid thermally overloading the emp891x, refrain from exceeding the absolute maximum junction temperature rating of 150c under continuous operating conditions. overstressing the regulator with high loading currents and elevated input-to-output differential voltages can increase the ic die temperature significantly. fault detection in the event of the occurrence of various fault conditions that cause failure in the output voltage regulation, such as during thermal overload or current limit, the fault pin of the emp891x becomes low. because the fault pin connects to the open-drain output of a n-channel mos transistor, a large pull-up resistor (100k typical) is required to provide the necessary output voltage and yet without compromising the overall power consumption performance of the regulator. the fault pin also goes low when the input-to-output differential voltage becomes too small to sustain good load and line regulation at the output. this occurs typically during near dropout when the input-to-output differential voltage is less than 95mv for a load current of 150ma. the emp891x detects near dropout conditions by comparing the differential voltage against a predefined differential threshold that is always slightly above the dropout voltage. this differential threshold is dynamical in the sense that it not only tracks the dropout voltage as the load current varies, but also scale linearly with the load current. shutdown when the shdn pin is low, the emp891x enters the sleep mode. when this occurs, the pass transistor, the error amplifier, and the biasing circuits, including the bandgap reference, are turned off, thus reducing the application information (continued) supply current to typically 1na. such a low supply
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 16/21 current makes the emp891x an ideal device for battery-powered applications. the maximum guaranteed voltage at the shdn pin for the sleep mode to take effect is 0.4v. a minimum guaranteed voltage of 1.2v at the shdn pin activates the emp891x. direct connection of the shdn pin to the v in to keep the regulator on is allowed for the emp891x. the shdn pin must not exceed the supply voltage v in under all conditions. fast start-up fast start-up time is one of the important factors for overall system efficiency improvement. the emp891x has a fast start-up speed when using the optional noise bypass capacitor (c cc ). to shorten start-up time, the emp891x internally supplies a 500a current to charge up the capacitor until it reaches about 95% of its final value.
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 17/21 physical dimensions sot-25 o 2 symbpls min. nom. max. a 1.05 1.20 1.35 a1 0.05 0.10 0.15 a2 1.00 1.10 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 2.90 3.00 e 2.60 2.80 3.00 e1 1.50 1.60 1.70 e 0.95 bsc e1 1.90 bsc l 0.30 0.45 0.55 l1 0.60 ref 0 5 10 2 6 8 10 unit: mm
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 18/21 sot-26 o 2 symbpls min. nom. max. a 1.45 a1 0.15 a2 0.9 1.15 1.3 b 0.3 0.5 c 0.08 0.22 d 2.90 bsc. e 2.80 bsc. e1 1.60 bsc. e 0.95 bsc e1 1.90 bsc l 0.3 0.45 0.6 l1 0.60 ref l2 0.25 ref 0 4 8 2 5 10 15 unit: mm
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 19/21 tdfn-6 common dimensions millimeter dimensions inch symbol min. nom. max. min. nom. max. a 0.70 0.75 0.80 0.027 0.029 0.031 a3 0.200 ref 0.008 ref b 0.25 0.30 0.35 0.010 0.012 0.014 d 2.00 bsc 0.079 bsc d2 1.20 1.30 1.40 0.046 0.050 0.054 e 2.00 bsc 0.079 bsc e2 0.50 0.60 0.70 0.022 0.024 0.026 e 0.650 bsc 0.026 bsc l 0.25 0.30 0.35 0.009 0.011 0.013
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 20/21 revision history revision date description 5.0 2009.03.24 emp transferred from version 4.1
esmt/emp emp891x elite semiconductor memory technology inc. publication date: mar. 2009 revision : 5.0 21/21 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the right to change the produ cts or specification in this document without notice. the information contained h erein is presented only as a guide or examples for the application of our products. no res ponsibility is assumed by esmt for any infringement of patents, co pyrights, or other intellect ual property rights of third parties which may result from its use. no license, either express, implied or otherwise, is granted under any patent s, copyrights or other intellectual property rights of esmt or others. any semiconductor devices may have inher ently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer w hen making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support device s or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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